This application claims the priority benefit of Taiwan application Ser. No. 87120925, filed Dec. 16, 1998.
1. Field of Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to a method for fabricating metal interconnects.
2. Description of Related Art
With the increase of integration in integrated circuits (IC), a conventional wafer can no longer provide sufficient area for interconnects. In order to satisfy performance requirements, design rules for forming more than two metal layers for interconnects are gradually applied in integrated circuits. Therefore, in current very large scale integration (VLSI) processes, difficulty of fabricating metal interconnects with better reliability and good conductivity is gradually increasing. At present, aluminum is commonly used as an interconnect material. Copper can provide good conductivity in a small contact surface, therefore, with the increasing integration in semiconductor devices, copper with low resistivity is gradually replacing aluminum.
Copper has advantages of low resistivity, high electromigration resistance, and a high melting point (melting point of copper is about 1060xc2x0 C., and melting point of aluminum is about 660xc2x0 C.). A conductive line made of copper can provide better performance than an aluminum conductive line, and reduces RC delay time. However, at this time, a better method of etching copper conductive lines has not found so as to restrict the use of copper.
One conventional method for solving the aforementioned problems is to form a dielectric layer over a substrate after a plug is formed. The dielectric layer is as thick as a desired metal line. The dielectric layer is defined to form an opening in the dielectric layer. The opening is filled with a conductive layer to form a metal line.
Another method is to simultaneously form a via hole and an opening. A conductive layer is deposited to fill the via hole and the opening. A metal interconnect is formed. Since these solution methods do not directly etch the metal line, the methods can overcome the difficulty of etching a metal line made of copper.
FIGS. 1A through 1C are schematic, cross-sectional views showing a conventional method of fabricating metal interconnects.
As shown in FIG. 1A, a semiconductor substrate 100 is provided, and preformed devices such as transistors (not shown) are formed on the substrate 100. An insulating layer (not shown) is formed over the substrate 100. A copper layer 102 is formed over the insulating layer as a conductive line. A silicon nitride layer 104 and an inter-metal dielectric layer (IMD) 106 are subsequently formed on the copper layer 102 by chemical vapor deposition (CVD). Another silicon nitride layer 108 and another inter-metal dielectric layer 110 are subsequently formed on the inter-metal dielectric layer 106. The silicon nitride layer 108 and the inter-metal dielectric layer 110 are defined to form openings 112, 114 until the inter-metal dielectric layer 106 is exposed.
As shown in FIG. 1B, the inter-metal dielectric layer 106 and the silicon nitride layer 104 are defined to form a via hole 116 below the opening 114 until the copper layer 102 is exposed. The definition step includes forming a patterned photoresist layer 118 over the substrate 100. A portion of the inter-metal dielectric layer 106 and the silicon nitride layer 106 are anisotropically etched to form the via hole 116.
As shown in FIG. 1C, the photoresist layer 118 (FIG. 1B) is removed. A conformal tantalum nitride layer 120 is formed over the substrate 100. Since adhesion between copper and dielectrics is poor, and copper atoms hastened by an electric field diffuse through the dielectric layers, the tantalum nitride layer 120 is formed as a glue/barrier layer to increase adhesion between copper and dielectric layers, and to stop the diffusion of copper atoms. A copper layer 122 is formed on the tantalum nitride layer 120 to fill the via hole 116 and the openings 112, 114. Using the inter-metal dielectric layer 110 as an etching end point, a portion of the copper layer 122 is removed by chemical-mechanical polishing (CMP). At this step, a metal interconnect is formed.
In the aforementioned process, the tantalum nitride layer 120 is used as a barrier layer to stop copper atoms and copper ions from diffusing into the inter-metal dielectric layer 106. But while forming the via hole 116, the inter-metal dielectric layer 106 and the silicon nitride layer 104 are anisotropically etched to expose the copper layer 102; at that time the tantalum nitride layer 120 is not yet formed. The silicon nitride layer 104 is continuously over-etched so that a portion of copper atoms or copper ions 102a is disassociated from the surface of the exposed copper layer 102, as seen in FIG. 1B. The copper atoms and copper ions easily remain at the via hole 116 bottom and on the via hole 116 sidewalls so that the chance of contamination by copper atoms or copper ions 102a (FIG. 1B) is thus increased. Moreover, after the etching step, a cleaning step is performed to clean the remaining etchants. The copper atoms or copper ions 102a (FIG. 1B) remaining at the via hole 116 bottom are taken out to the via hole 116 and the opening 114 by the cleaning step so that the copper atoms or copper ions 102a (FIG. 1B) remain on the sidewalls of the via hole 116 and the opening 114. Since, in this step, the inter-metal dielectric layers 106 and 110 are not yet covered with the tantalum nitride layer 120, the copper atoms (or copper ions) 120a diffuse into the inter-metal dielectric layers 106 and 110. Thus, in a later thermal process, copper atoms (or copper ions) 120a would diffuse in the inter-metal dielectric layer 106 more rapidly and more deeply, further diffusing into preformed devices on the substrate 100 and contaminating the substrate 100, leading to changed device properties. In addition, unexpected electrical connection caused by the diffusion of the copper atoms or copper ions is generated between two isolated metal layers so as to decrease reliability of the metal interconnects.
Accordingly, the purpose of the present invention is to provide a method for fabricating metal interconnects. The method can avoid contaminating devices on a substrate with copper atoms or copper ions so as to increase reliability and performance of devices. In addition, unexpected electrical connection between two dielectric layers caused by the diffusion of the copper atoms or copper ions can also be avoided.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for fabricating metal interconnects on a semiconductor substrate. The method comprises sequentially forming a copper layer, a first stop layer, a first inter-metal dielectric layer, a second stop layer, and a second inter-metal dielectric layer over the substrate. The second inter-metal dielectric layer and the second stop layer are defined to form an opening. A conformal first glue/barrier layer is formed over the substrate. The first glue/barrier layer and the first inter-metal dielectric layer are defined to form a via hole below the opening until the first stop layer is exposed. Spacers are formed on sidewalls of the opening and the via hole below the opening. The first stop layer at bottom of the via hole is removed to expose the copper layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.